View MSM51V8221A-40GS-K_6903251.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
1/16 ? semiconductor msm51v8221a description the oki msm51v8221a is a high performance 2-mbit, 256k 8-bit, field memory. it is designed for high-speed serial access applications such as hdtvs, conventional ntsc tvs, vtrs, digital movies and multi-media systems. it is a fram for wide or low end use as general commodity tvs and vtrs, exclusively. the msm51v8221a is not designed for the other use or high end use in medical systems, professional graphics systems which require long term picture, and data storage systems and others. the 2-mbit capacity fits one field of a conventional ntsc tv screen. each of the 8-bit planes has separate serial write and read ports. these employ independent control clocks to support asynchronous read and write operations. different clock rates are also supported, which allow alternate data rates between write and read data streams. the msm51v8221a provides high speed fifo, first-in first-out, operation without external refreshing: it refreshes its dram storage cells automatically, so that it appears fully static to the users. moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. the msm51v8221a's function is simple, and similar to a digital delay device whose delay-bit-length is easily set by reset timing. the delay length, and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. additional sram serial registers, or line buffers for the initial access of 256 8-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings. the msm51v8221a is similar in operation and functionality to oki 1-mbit field memory msm51v4221c. it has a write mask function or input enable function (ie), and read-data skipping function or output enable function (oe). the differences between write enable (we) and input enable (ie), and between read enable (re) and output enable (oe) are that we and re can stop serial write/read address increments, but ie and oe cannot stop the increment, when write/read clocking is continuously applied to msm51v8221a. the input enable (ie) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. this facilitates data processing to display a "picture in picture" on a tv screen. ? semiconductor msm51v8221a 262,214-word 8-bit field memory e2l0054-28-z2 this version: dec. 1998 previous version: mar. 1998
2/16 ? semiconductor msm51v8221a features ? single power supply : 3.3 v 0.3 v ? 512 rows 512 columns 8 bits ? fast fifo (first-in first-out) operation ? high speed asynchronous serial access read/write cycle time 30 ns/40 ns access time 30 ns/35 ns ? functional compatibility with oki msm51v4221c ? write mask function (input enable control) ? data skipping function (output enable control) ? self refresh (no refresh control is required) ? package options : 28-pin 400 mil plastic zip (zip28-p-400-1.27) (product : msm51v8221a-xxzs) 28-pin 400 mil plastic soj (soj28-p-400-1.27) (product : msm51v8221a-xxjs) 28-pin 430 mil plastic sop (sop28-p-430-1.27-k) (product : msm51v8221a-xxgs-k) xx indicates speed rank. product family msm51v8221a-30js family access time (max.) cycle time (min.) package 30 ns 30 ns 400 mil 28-pin soj msm51v8221a-40js 40 ns 35 ns msm51v8221a-30zs 30 ns 30 ns 400 mil 28-pin zip msm51v8221a-40zs 40 ns 35 ns msm51v8221a-30gs-k 30 ns 30 ns 430 mil 28-pin sop MSM51V8221A-40GS-K 40 ns 35 ns
3/16 ? semiconductor msm51v8221a d in 4 d in 5 d in 6 d in 7 rstw swck nc re oe d out 7 d out 6 d out 5 d out 4 v ss v cc d in 3 d in 2 d in 1 d in 0 ie we nc srck rstr d out 0 d out 1 d out 2 d out 3 d in 4 d in 5 d in 6 d in 7 rstw swck nc re oe d out 7 d out 6 d out 5 d out 4 v ss v cc d in 3 d in 2 d in 1 d in 0 ie we nc srck rstr d out 0 d out 1 d out 2 d out 3 28-pin plastic zip 1 3 5 7 9 11 13 15 17 19 21 23 25 27 we d in 0 d in 2 v cc d in 5 d in 7 swck nc oe d out 6 d out 4 d out 3 d out 1 rstr 2 4 6 8 10 12 14 16 18 20 22 24 26 28 ie d in 1 d in 3 d in 4 d in 6 rstw nc re d out 7 d out 5 v ss d out 2 d out 0 srck 3 4 5 9 10 11 12 13 26 25 24 20 19 18 17 16 2 27 1 28 28-pin plastic soj 3 4 5 9 10 11 12 13 26 25 24 20 19 18 17 16 2 27 1 28 28-pin plastic sop 623 23 821 21 6 8 722 22 7 14 15 14 15 pin configuration (top view) pin name function serial write clock serial read clock write enable read enable input enable output enable write reset clock read reset clock data input data output power supply (3.3 v) ground (0 v) swck srck we re ie oe rstw rstr d in 0 - 7 d out 0 - 7 v cc v ss nc no connection
4/16 ? semiconductor msm51v8221a block diagram d out ( 8) data-out buffer ( 8) oe re rstr srck serial 512-word serial read register ( 8) read line buffer low-half ( 8) read line buffer high-half ( 8) 256 ( 8) 256k ( 8) memory array x decoder 71-word sub-register ( 8) read/write and refresh controller clock oscillator write line buffer low-half ( 8) write line buffer high-half ( 8) 512-word serial write register ( 8) data-in buffer ( 8) d in ( 8) serial ie we rstw swck 71-word sub-register ( 8) 256 ( 8) 256 ( 8) 256 ( 8) v bb generator read controller write controller
5/16 ? semiconductor msm51v8221a operation write operation the write operation is controlled by three clocks, swck, rstw, and we. write operation is accomplished by cycling swck, and holding we high after the write address pointer reset operation or rstw. each write operation, which begins after rstw, must contain at least 80 active write cycles, i.e. swck cycles while we is high. to transfer the last data to the dram array, which at that time is stored in the serial data registers attached to the dram array, an rstw operation is required after the last swck cycle. write reset : rstw the first positive transition of swck after rstw becomes high resets the write address counters to zero. rstw setup and hold times are referenced to the rising edge of swck. because the write reset function is solely controlled by the swck rising edge after the high level of rstw, the states of we and ie are ignored in the write reset cycle. before rstw may be brought high again for a further reset operation, it must be low for at least two swck cycles. data inputs : d in 0 - 7 write clock : swck the swck latches the input data on chip when we is high, and also increments the internal write address pointer. data-in setup time t ds , and hold time t dh are referenced to the rising edge of swck. write enable : we we is used for data write enable/disable control. we high level enables the input, and we low level disables the input and holds the internal write address pointer. there are no we disable time (low) and we enable time (high) restrictions, because the msm51v8221a is in fully static operation as long as the power is on. note that we setup and hold times are referenced to the rising edge of swck. input enable : ie ie is used to enable/disable writing into memory. ie high level enables writing. the internal write address pointer is always incremented by cycling swck regardless of the ie level. note that ie setup and hold times are referenced to the rising edge of swck.
6/16 ? semiconductor msm51v8221a read operation the read operation is controlled by three clocks, srck, rstr, and re. read operation is accomplished by cycling srck, and holding re high after the read address pointer reset operation or rstr. each read operation, which begins after rstr, must contain at least 80 active read cycles, i.e. srck cycles while re is high. read reset : rstr the first positive transition of srck after rstr becomes high resets the read address counters to zero. rstr setup and hold times are referenced to the rising edge of srck. because the read reset function is solely controlled by the srck rising edge after the high level of rstr, the states of re and oe are ignored in the read reset cycle. before rstr may be brought high again for a further reset operation, it must be low for at least two srck cycles. data out : d out 0 - 7 read clock : srck data is shifted out of the data registers. it is triggered by the rising edge of srck when re is high during a read operation. the srck input increments the internal read address pointer when re is high. the three-state output buffer provides direct ttl compatibility (no pullup resistor required). data out is the same polarity as data in. the output becomes valid after the access time interval t ac that begins with the rising edge of srck. there are no output valid time restrictions on msm51v8221a. read enable : re the function of re is to gate of the srck clock for incrementing the read pointer. when re is high before the rising edge of srck, the read pointer is incremented. when re is low, the read pointer is not incremented. re setup times (t rens and t rdss ) and re hold times (t renh and t rdsh ) are referenced to the rising edge of the srck clock. output enable : oe oe is used to enable/disable the outputs. oe high level enables the outputs. the internal read address pointer is always incremented by cycling srck regardless of the oe level. note that oe setup and hold times are referenced to the rising edge of srck.
7/16 ? semiconductor msm51v8221a power-up and initialization on power-up, the device is designed to begin proper operation after at least 100 m s after v cc has stabilized to a value within the range of recommended operating conditions. after this 100 m s stabilization interval, the following initialization sequence must be performed. because the read and write address counters are not valid after power-up, a minimum of 80 dummy write operations (swck cycles) and read operations (srck cycles) must be performed, followed by an rstw operation and an rstr operation, to properly initialize the write and the read address pointer. dummy write cycles/rstw and dummy read cycles/rstr may occur simultaneously. if these dummy read and write operations start while v cc and/or the substrate voltage has not stabilized, it is necessary to perform an rstr operation plus a minimum of 80 srck cycles plus another rstr operation, and an rstw operation plus a minimum of 80 srck cycles plus another rstw operation to properly initialize read and write address pointers. old/new data access there must be a minimum delay of 600 swck cycles between writing into memory and reading out from memory. if reading from the first field starts with an rstr operation, before the start of writing the second field (before the next rstw operation), then the data just written will be read out. the start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 70 swck cycles. if the rstr operation for the first field read-out occurs less than 70 swck cycles after the rstw operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. the first field of data that is read out while the second field of data is written is called "old data". in order to read out "new data", i.e., the second field written in, the delay between an rstw operation and an rstr operation must be at least 600 srck cycles. if the delay between rstw and rstr operations is more than 71 but less than 600 cycles, then the data read out will be undetermined. it may be "old data" or "new" data, or a combination of old and new data. such a timing should be avoided.
8/16 ? semiconductor msm51v8221a parameter unit input capacitance (d in , swck, srck, rstw, rstr, we, re, ie, oe) output capacitance (d out ) pf pf c i c o 7 7 symbol max. (ta = 25c, f = 1 mhz) electrical characteristics absolute maximum ratings parameter symbol condition rating input output voltage output current power dissipation operating temperature storage temperature v t i os p d t opr t stg at ta = 25c, v ss ta = 25c ta = 25c C1.0 to 4.6 50 1 0 to 70 C55 to 150 unit v ma w c c recommended operating conditions parameter symbol min. unit typ. max. power supply voltage power supply voltage input high voltage input low voltage v cc v ss v ih v il v v v v 3.0 0 2.4 C0.3 3.3 0 v cc 0 3.6 0 v cc + 0.3 0.8 dc characteristics parameter symbol condition min. input leakage current output leakage current output "h" level voltage output "l" level voltage operating current standby current i li i lo v oh v ol i cc1 i cc2 minimum cycle time, output open C10 C10 2.4 max. unit 10 10 0.4 35 3 m a m a v v ma ma 0 < v i < v cc + 0.3 v, other pins tested at v = 0 v 0 < v o < v cc i oh = C1 ma i ol = 2 ma input pin = v ih / v il capacitance
9/16 ? semiconductor msm51v8221a ac characteristics 6 6 12 12 5 6 4 5 0 5 4 5 0 10 10 10 0 10 12 12 0 5 0 5 0 5 30 30 access time from srck d out hold time from srck d out enable time from srck swck "h" pulse width swck "l" pulse width input data setup time input data hold time we enable setup time we enable hold time we disable setup time we disable hold time ie enable setup time ie enable hold time ie disable setup time we "h" pulse width ie "h" pulse width ie "l" pulse width rstw setup time rstw hold time srck "h" pulse width srck "l" pulse width re enable setup time re enable hold time re disable setup time re disable hold time oe enable setup time oe enable hold time symbol unit max. min. parameter msm51v8221a-40 ns (v cc = 3.3 v 0.3 v, ta = 0c to 70c) max. min. msm51v8221a-30 6 6 17 17 5 6 4 5 0 5 4 5 0 10 10 10 0 10 17 17 0 5 0 5 0 5 35 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 ie disable hold time 5ns 10 we "l" pulse width 10 ns 0 5 10 10 10 10 0 oe disable setup time oe disable hold time re "h" pulse width re "l" pulse width oe "h" pulse width oe "l" pulse width rstr setup time ns 0 5 10 10 10 10 0 ns ns ns ns ns ns 10 rstr hold time 10 ns 30 t ac t ddck t deck t wswh t wswl t ds t dh t wens t wenh t wdss t wdsh t iens t ienh t idss t wweh t wieh t wiel t rstws t rstwh t wsrh t wsrl t rens t renh t rdss t rdsh t oens t oenh t idsh t wwel t odss t odsh t wreh t wrel t woeh t woel t rstrs t rstrh t swc swck cycle time 40 ns 30 t src srck cycle time 40 ns 3 t t transition time (rise and fall) 3 ns 30 30
10/16 ? semiconductor msm51v8221a notes: 1. input signal reference levels for the parameter measurement are v ih = 3.0 v and v il = 0 v. the transition time t t is defined to be a transition time that signal transfers between v ih = 3.0 v and v il = 0 v. 2. ac measurements assume t t = 3 ns. 3. read address must have more than a 600 address delay than write address in every cycle when asynchronous read/write is performed. 4. read must have more than a 600 address delay than write in order to read the data written in a current series of write cycles which has been started at last write reset cycle: this is called "new data read". when read has less than a 70 address delay than write, the read data are the data written in a previous series of write cycles which had been written before the last write reset cycle: this is called "old data read". 5. when the read address delay is between more than 71 and less than 599, read data will be undetermined. however, normal write is achieved in this address condition. 6. outputs are measured with a load equivalent to 1 ttl load and 30 pf. output reference levels are v oh = 2.0 v and v ol = 0.8 v.
11/16 ? semiconductor msm51v8221a timing waveform write cycle timing (write reset) swck rstw d in we v ih v il ie v ih v il v ih v il v ih v il v ih v il n cycle 0 cycle 1 cycle 2 cycle t t t rstws t rstwh t wswh t wswl t swc t dh t ds n0123 write cycle timing (write enable) swck rstw d in we v ih v il ie v ih v il v ih v il v ih v il v ih v il n cycle disable cycle disable cycle n+1 cycle t wenh t wdsh t wdss t wens t wwel t wweh n n+2 n+1
12/16 ? semiconductor msm51v8221a write cycle timing (input enable) swck rstw d in we v ih v il ie v ih v il v ih v il v ih v il v ih v il n cycle n+1 cycle n+2 cycle n+3 cycle t ienh t idsh t idss t iens t wieh t wiel n n+4 n+3 read cycle timing (read reset) srck rstr d out re v oh v ol oe v ih v il v ih v il v ih v il v ih v il n cycle 0 cycle 1 cycle 2 cycle t t t rstrs t rstrh t wsrh t wsrl t src t ac t ddck n-1n0 12
13/16 ? semiconductor msm51v8221a read cycle timing (read enable) srck rstr d out re v oh v ol oe v ih v il v ih v il v ih v il v ih v il n cycle disable cycle disable cycle n+1 cycle t renh t rdsh t rdss t rens t wreh t wrel n-1 n n+1 read cycle timing (output enable) srck rstr d out oe v oh v ol re v ih v il v ih v il v ih v il v ih v il n cycle n+1 cycle n+2 cycle n+3 cycle t oenh t odsh t odss t oens t woen t woeh t deck n-1 n n+3 hi-z
14/16 ? semiconductor msm51v8221a (unit : mm) package dimensions zip28-p-400-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.85 typ. mirror finish
15/16 ? semiconductor msm51v8221a (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj28-p-400-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.30 typ. mirror finish
16/16 ? semiconductor msm51v8221a (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). sop28-p-430-1.27-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.75 typ. mirror finish
notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 1998 oki electric industry co., ltd. printed in japan e2y0002-28-41

▲Up To Search▲

Price & Availability of MSM51V8221A-40GS-K

	To Download MSM51V8221A-40GS-K Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .